View W78CE354_4403807.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

p reliminary w78c354 monitor microcontroller publication release date: october 1996 - 1 - revision a1 general description the w78c354 is a high-performance monitor microcontroller that is based on the embedded 80c32 microcontroller core. the w78c354 includes a 16 kb rom, 512 byte internal data ram, a 6-bit a/d converter, two 12-bit and fourteen 8-bit pwm static dacs, one 12-bit and three 8-bit pwm dynamic dacs, a sync processor, an i 2 c port, a ddc port, a watchdog timer, and glue logic specially designed for monitor applications. the w78c354 is suitable for monitors applying vesa ddc1/ddc2b/ddc2b+. this product's high level of integration and the availability of a one-time programmable (otp) flash prom version(the w78e354) help to reduce unit costs, development costs, and development time. features 80c32 mcu core included 20 mhz maximum operating frequency 16 kb rom for program storage 512 bytes of on-chip data ram: - lower 256 bytes accessed as in the 80c32 - higher 256 bytes accessed as an external data memory via "movx @ri". one spi/rs232 port (80c32 standard serial port) one external interrupt input two timers/counters one 8-bit auto-reload timer for software time base pwm dacs: - two 12-bit pwm/brm static dacs - fourteen 8-bit pwm static dacs - one 12-bit pwm/brm dynamic dac - three 8-bit pwm dynamic dacs one 6-bit adc with 4 multiplexed analog inputs sync processor: - horizontal & vertical polarity detector - sync separator for composite sync - horizontal & vertical frequency counter - programmable dummy frequency generator - programmable h-clamp pulse output - safe operation area (soa) output - self-test pattern output one software i 2 c port one ddc port (master/slave mode i 2 c, supports ddc1/ddc2b/ddc2b+) watchdog timer moire cancellation two 15 ma output pins for driving led power-low reset otp type: w78e354 (16 kb flash prom) three package types: - plcc68 (w78c/e354p), dip48 (w78c/e354e), dip40 (w78c/e354)
w78c354 - 2 - pin configurations w78c/e354p (plcc68) sdac10 10 14 13 12 11 16 15 17 21 20 19 18 23 22 24 26 25 60 56 57 58 59 54 55 53 49 50 51 52 47 48 46 44 45 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 61 62 63 64 65 66 67 68 1 2 3 4 5 6 7 8 9 sdac11 p2.6 p2.7 oscout oscin vss p2.0 p2.1 sdac12 sdac13 p2.2 p2.3, stp p3.4, t0 p3.5, t1 hin vin h o u t v o u t b s d a c 0 b s d a c 1 p 3 . 0 , r x d p 3 . 1 , t x d / r s t v s s v s s a a d c 0 a d c 1 v a a a d c 2 , p 1 . 6 a d c 3 , p 1 . 7 n c p 3 . 2 , i n t 0 p 3 . 6 p4.0 p4.1 p1.0, iscl p1.1, isda p1.2, dscl ddac1 ddac2 bddac sdac0 p4.2 vpp p4.3 ddac0 (only for w78e354p) vdd p1.5, soa p1.4, hclamp p1.3, dsda p 3 . 3 s d a c 1 s d a c 2 p 4 . 4 s d a c 3 s d a c 4 p 3 . 7 v d d p 4 . 5 p 4 . 6 s d a c 5 s d a c 6 s d a c 7 s d a c 8 s d a c 9 p 2 . 4 p 2 . 5 vdd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 47 48 42 43 44 45 46 38 39 40 41 34 35 36 37 29 30 31 32 33 sdac4 sdac3 sdac2 sdac1 p3.3 sdac0 bddac ddac2 ddac1 ddac0 vpp p1.3, dsda p1.4, hclamp p1.5, soa p3.2, int0 p3.6 p1.0, iscl p1.1, isda p1.2, dscl sdac5 sdac7 p2.4, sdac10 p2.0 oscout oscin p2.1 p2.2 p2.3, stp p3.4, t0 p3.5, t1 hin hout vin vout sdac6 vdd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 39 40 34 35 36 37 38 30 31 32 33 26 27 28 29 21 22 23 24 25 sdac4 sdac3 sdac2 sdad1 sdad0 bddac ddac0 vpp p1.5, soa p1.4, hclamp p1.3, dsda p1.0, iscl p1.1, isda p1.2, dscl p3.1, txd rst adc0 nc p3.2, int0 sdac5 sdac7 p2.4, sdac10 p2.5, sdac11 p2.6, sdac12 p2.7, sdac13 vss p2.0 oscout oscin p2.1 p2.2 p2.3, stp hin vin hout bsdac0 vout p3.0, rxd sdac6 vssa adc0 vaa nc bsdac0 p3.1, txd p3.0, rxd rst 21 22 23 24 28 27 26 25 p2.5, sdac11 p2.6, sdac12 p2.7, sdac13 vss (only for w78e354e) (only for w78e354) w78c/e354e (dip48) w78c/e354 (dip40)
w78c354 publication release date: october 1996 - 3 - revision a1 pin arrangement reference table dip-40 dip-48 plcc-68 pin name dip-40 dip-48 plcc-68 pin name 22 24 33 rst - - 37 adc1 15 17 25 hin - - 39 adc2(p1.6) 16 18 26 vin - - 40 adc3(p1.7) 17 19 27 hout - 27 38 v aa 18 20 28 vout - 25 35 v ssa 35 42 60 sdac0 11 11 17 p2.0 36 44 62 sdac1 12 12 18 p2.1 37 45 63 sdac2 13 13 21 p2.2 38 46 65 sdac3 14 14 22 p2.3 (stp) 39 47 66 sdac4 4 4 8 p2.4 (sdac10) 1 1 3 sdac5 5 5 9 p2.5 (sdac11) 2 2 4 sdac6 6 6 12 p2.6 (sdac12) 3 3 5 sdac7 7 7 13 p2.7 (sdac13) - - 6 sdac8 20 22 31 p3.0 (rxd ) - - 7 sdac9 21 23 32 p3.1 (txd ) - - 10 sdac10 25 29 42 p3.2 (int0) - - 11 sdac11 - 43 61 p3.3 - - 19 sdac12 - 15 23 p3.4 (t0) - - 20 sdac13 - 16 24 p3.5 (t1) 19 21 29 bsdac0 - 30 43 p3.6 - - 30 bsdac1 - - 67 p3.7 40 48 68 v dd - - 44 p4.0 10 10 16 v ss - - 45 p4.1 34 41 59 bddac - - 53 p4.2 33 38 56 ddac0 - - 55 p4.3 - 39 57 ddac1 - - 64 p4.4 - 40 58 ddac2 - - 1 p4.5 26 31 46 p1.0 (iscl) - - 2 p4.6 27 32 47 p1.1 (isda) 24 28 41 nc 28 33 48 p1.2 (dscl) 32 37 54 v pp 29 34 49 p1.3 (dsda) - - 52 v dd 30 35 50 p1.4 (hclamp) - - 34 v ss 31 36 51 p1.5 (soa) 8 8 14 oscout 23 26 36 adc0 9 9 15 oscin
w78c354 - 4 - pin description pin name i/o type function sdac0 - 7 o 8-bit pwm static dac output. sink/source current 4 ma/-4 ma. sdac8 - 13 o 8-bit pwm static dac output. sink/source current 4 ma/-4 ma. bsdac0 - 1 o 12-bit pwm/brm static dac output. sink/source current 8 ma/-8 ma. ddac0 - 2 o 8-bit pwm dynamic dac output. sink/source current 8 ma/-8 ma. bddac o 12-bit pwm/brm dynamic dac output. sink/source current 8 ma/-8 ma. adc0 adc1 adc2 (p1.6) adc3 (p1.7) i analog signal input channel to ad converter. alternate function: adc2: p1.6 input (input only). adc3: p1.7 input (input only). p1.0 - p1.1 i/o general purpose i/o. open-drain, sink current 2 ma. p1.2 (dscl) p1.3 (dsda) i/o general purpose i/o. open-drain, sink current 6 ma. alternate function: p1.2: ddc port serial clock dscl. p1.3: ddc port serial data dsda. p1.4 (hclamp) i/o general purpose i/o. sink/source current 4 ma/-100 m a. alternate function: p1.4: hclamp (h-clamp pulse) output. while outputing special function, p1.4 sink/source current is 4 ma/-4 ma. p1.5 (soa) i/o general purpose o/p. sink/source current 4 ma/-4 ma. alternate function: p1.5: soa (safe operation area) output. p2.0 - p2.1 i/o general purpose i/o. sink/source current 15 ma/-100 m a.
w78c354 publication release date: october 1996 - 5 - revision a1 pin description, continued pin name i/o type function p2.2 p2.3 ( stp) p2.4 (sdac10) p2.5 (sdac11) p2.6 (sdac12) p2.7 (sdac13) i/o general purpose i/o. sink/source current 4 ma/-100 m a. alternate function: p2.3: stp (self-test pattern) output. p2.4 - p2.7: sdac10 - 13 outputs. while outputing special function, p2.3 - p2.7 sink/source current is 4 ma/-4 ma. p3.0 (rxd) p3.1 (txd) p3.2 (int0) p3.3 p3.4 (t0) p3.5 (t1) p3.6 p3.7 i/o general purpose i/o. sink/source current 2 ma/-100 m a. alternate function: p3.0: serial input port. p3.1: serial output port. p3.2: external interrupt input. p3.4, p3.5: timer/counter 0, 1 external inputs. p4.0 - p4.6 o output port. sink/source current 2 ma/-2 ma. hin vin i hin: hsync/composite sync input. vin: vsync input. schmitt trigger input pin. hout vout o hout: hsync output. vout: vsync output. sink/source current 4 ma/-4 ma. rst i reset the controller (active low). schmitt trigger input pin. oscout o output from inverting oscillator amplifier. oscin i input to inverting oscillator amplifier. v pp i high voltage supply input for flash prom. v dd i positive power supply for digital circuit, +5v. v ss i digital ground. v aa i positive power supply for analog circuit, +5v. v ssa i analog ground. block diagram
w78c354 - 6 - cpu core 16k x 8 mask rom 512 x 8 ram power source supervisor serial port wdt timer0 timer1 txd rxd v v rst sdac ddac adc sdac0 to 13, bsdac0 to 1 ddac0 to 2, bddac adc0 to 3 isda iscl ddc port dsda dscl interrupt processor p2 p4 i/o port int0 t0 t1 oscillator sync. processor hout, vout hin, vin hclamp reset circuit auto reload timer soa dd v aa v , i ss 2 c ssa
w78c354 publication release date: october 1996 - 7 - revision a1 functional description the w78c354's core architecture consists of an 80c32 mcu surrounded by various special function registers, or sfrs (some of these are 80c32 standard registers, while others are newly added; see table 1), three general purpose i/o ports (p1, p2, and p3), one output-only port (p4), 256 bytes of scratchpad ram, two timer/counters (timer0 and timer1) and one 80c32 standard serial port. the processor supports 109 different instructions (without "movx a, @dptr" and "movx @dptr, a"), which are all compatible with the 80c32 family instruction set. there are two major differences between the w78c354 and 80c32. first, the w78c354 cannot access an external program or data memory. this function is unnecessary, because the w78c354's 16 kb of internal rom and 512 bytes of on-chip ram should be enough for most monitor applications. second, the w78c354 has a number of new sfrs (see table 2), which provide more powerful functions. table 1. w78c354 special function registers (sfrs) f8 ff f0 + b f7 e8 ef e0 + acc e7 d8 + s1con s1sta s1dat s1adr df d0 + psw d7 c8 + contreg4 cf c0 c7 b8 + ip sbrm0 sbrm1 port4 soareg soaclr bf b0 + p3 adc intvect status hfcountl hfcounth vfcountl vfcounth b7 a8 + ie sdac7 sdac8 sdac9 sdac10 sdac11 sdac12 sdac13 af a0 + p2 sdac0 sdac1 sdac2 sdac3 sdac4 sdac5 sdac6 a7 98 + scon sbuf bsdac0 bsdac1 wdtclr ddac0 ddac1 ddac2 9f 90 + p1 autoload dhreg dvreg ddc1 intmsk bddac dbrm 97 88 + tcon tmod tl0 tl1 th0 th1 paral parah 8f 80 + contreg1 sp dpl dph contreg5 contreg2 pcon 87 notes: 1. sfrs with a "+" are both byte and bit-addressable. 2. the registers in the shaded region are newly added to the 80c32. a. memory address space the w78c354 operates in three separate address spaces: (1) the first (figure 1-1) is the 16 kb internal program space (0000h - 3fffh). (2) the second (figure 1-2) is the data memory space, which is 256 bytes in size (0000h - 00ffh). the data memory is integrated inside the chip rather than outside the chip, as in a standard 80c32. this data memory space must be accessed by the "movx @ri" instruc tion. (3) the third (figure 1-3) is the same as in the standard 80c32.
w78c354 - 8 - 0000h 3fffh 00h ffh 00h on-chip program memory on-chip data memory ffh 7fh 80h (direct addressing) (direct/indirect addressing) sfr scratchpad ram (indirect addressing) scratchpad ram (movx @ri) figure 1-1 figure 1-3 figure 1-2 figure 1. memory address space b. modified 80c32 sfrs 1. timer/counter control register (tcon): bit name function tcon.7 tf1 timer 1 overflow flag. set by hardware on timer/counter overflow. c leared by hardware when processor vectors to interrupt routine. tcon.6 tr1 timer 1 run control bit. set/cleared by software to turn timer/counter on or off. tcon.5 tf0 timer 0 overflow flag. set by hardware on timer/counter overflow. c leared by hardware when processor vectors to interrupt routine. tcon.4 tr0 timer 0 run control bit. set/cleared by software to turn timer/counter on or off. tcon.3 - reserved tcon.2 - reserved tcon.1 ie0 interrupt 0 edge flag. set by hardware when external interrupt edge detected. cleared by hardware when interrupt processed. tcon.0 it0 interrupt 0 type control bit. set/cleared by software to specify falling edge/low level triggered external interrupt. note: the registers in the shaded region are modified from the 80c32 sfrs.
w78c354 publication release date: october 1996 - 9 - revision a1 2. power control register (pcon): name function smod double baud rate bit. - reserved - reserved - reserved gf1 general-purpose flag bit. gf0 general-purpose flag bit. - reserved idl idle mode bit. notes: 1. the sfr is not bit-addressable. 2. the registers in the shaded region are modified from the 80c32 sfrs. 3. interrupt enable register (ie): bit name function ie.7 ea if ea = 0, no interrupt will be acknowledged (disable all interrupt s ). if ea = 1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit. ie.6 - (reserved) ie.5 *1 set/clear to enable/disable the ddc port's i 2 c interrupt. ie.4 es set/clear to enable/disable the serial port 0 interrupt. ie.3 et1 set/clear to enable/disable the timer 1 overflow interrupt. ie.2 *1 set/clear to enable/disable the *2 interrupt. ie.1 et0 set/clear to enable/disable the timer 0 overflow interrupt. ie.0 ex0 set/clear to enable/disable the external interrupt 0. notes: *1. no name for assembler, must be used via "ie.x". ?. *2. dsclint+adcint+timeout+soaint+vevent+paraint +ddc1int.
w78c354 - 10 - 4. interrupt priority register (ip) bit name function ip.7 - (reserved) ip.6 - (reserved) ip.5 *1 define the ddc port's i 2 c interrupt priority level. if ip.5 = 1, the priority level is higher. ip.4 ps define the serial port interrupt priority level. if ps = 1, the priority level is higher. ip.3 pt1 define the timer 1 interrupt priority level. if pt1 = 1, the priority level is higher. ip.2 *1 define the *2 priority level. if ip.2 = 1, the priority level is higher. ip.1 pt0 define the timer 0 interrupt priority level. if pt0 = 1, the priority level is higher. ip.0 px0 define the external interrupt 0 priority level. if px0 = 1, the priority level is higher. notes: *1. no name for assembler, must be used via "ip.x". *2. dsclint+adcint+timeout+soaint+vevent+paraint+ddc1int. c. newly added special function registers in addition to the 80c32 sfrs, the w78c354 has forty-nine new sfrs in the sfr address space, as listed in table 2. table 2. new special function registers register address function length r/w type reset content 1 contreg1 80h control register 1, bit-addressable 8 r/w 00h 2 contreg5 84h control register 5 8 r/w 00h 3 contreg2 85h control register 2 8 w 00h 4 paral 8eh parabola interrupt generator low byte register 8 w 00h 5 parah 8fh parabola interrupt generator high byte register 8 w 00h 6 autoload 91h 8-bit auto-reload timer register 8 w 00h 7 dhreg 92h dummy hsync frequency generator register 4 w 00h 8 dvreg 93h dummy vsync frequency generator register 8 w 00h 9 ddc1 94h ddc port's ddc1 data buffer 8 w 00h 10 intmsk 95h interrupt mask register 8 w 00h 11 bddac 96h 8-bit pwm register for 12-bit pwm/brm dynamic dac 8 w 00h 12 dbrm 97h 4-bit brm register for 12-bit pwm/brm dynamic dac 4 w 00h
w78c354 publication release date: october 1996 - 11 - revision a1 table 2. new special function registers, continued register address function length r/w type reset content 13 bsdac0 9ah 8-bit pwm register for 12-bit pwm/brm static dac0 8 w 00h 14 bsdac1 9bh 8-bit pwm register for 12-bit pwm/brm static dac1 8 w 00h 15 wdtclr 9ch watch-dog timer clear register - w - 16 ddac0 9dh 8-bit pwm dynamic dac0 register 8 w 00h 17 ddac1 9eh 8-bit pwm dynamic dac1 register 8 w 00h 18 ddac2 9fh 8-bit pwm dynamic dac2 register 8 w 00h 19 sdac0 a1h 8-bit pwm static dac0 register 8 w 00h 20 sdac1 a2h 8-bit pwm static dac1 register 8 w 00h 21 sdac2 a3h 8-bit pwm static dac2 register 8 w 00h 22 sdac3 a4h 8-bit pwm static dac3 register 8 w 00h 23 sdac4 a5h 8-bit pwm static dac4 register 8 w 00h 24 sdac5 a6h 8-bit pwm static dac5 register 8 w 00h 25 sdac6 a7h 8-bit pwm static dac6 register 8 w 00h 26 sdac7 a9h 8-bit pwm static dac7 register 8 w 00h 27 sdac8 aah 8-bit pwm static dac8 register 8 w 00h 28 sdac9 abh 8-bit pwm static dac9 register 8 w 00h 29 sdac10 ach 8-bit pwm static dac10 register 8 w 00h 30 sdac11 adh 8-bit pwm static dac11 register 8 w 00h 31 sdac12 aeh 8-bit pwm static dac12 register 8 w 00h 32 sdac13 afh 8-bit pwm static dac13 register 8 w 00h 33 adc b1h 6-bit adc result register 8 r 00h 34 intvect b2h interrupt vector register 8 r/w 00h 35 status b3h status register 4 r 00h 36 hfcountl b4h horizontal frequency counter low byte register 8 r 00h 37 hfcounth b5h horizontal frequency counter high byte register 8 r 00h 38 vfcountl b6h vertical frequency counter low byte register 8 r 00h 39 vfcounth b7h vertical frequency counter high byte register 8 r 00h 40 sbrm0 b9h 4-bit brm register for 12-bit pwm/brm static dac0 4 w 00h 41 sbrm1 bah 4-bit brm register for 12-bit pwm/brm static dac1 4 w 00h 42 port4 bbh output latch register 7 w 00h 43 soareg bch safe operation area register 8 w 00h 44 soaclr bdh safe operation area clear register - w - 45 contreg4 c8h control register 4 8 r/w 00h 46 s1con d8h sio1 port control register 8 r/w 00h 47 s1sta d9h sio1 port status register 8 r f8h 48 s1dat dah sio1 port data register 8 r/w 00h 49 s1adr dbh sio1 port address register 8 r/w 00h notes: 1. "-" means the sfr has no real hardware but only an address. 2. three sfrs (contreg1, contreg4, sicon) can be accessed by bit addressing. d. status and control register overview 1. status: status register
w78c354 - 12 - bit name function 0 hp hsync polarity. 0: positive, 1: negative. 1 vp vsync polarity. 0: positive, 1: negative. 2 noh set by hardware if no hsync. 3 nov set by hardware if no vsync. 2. contreg1: control register1, bit-addressable bit name function 0 adcs0 adc channel select bit 0. 1 adcs1 adc channel select bit 1. 2 enddc1 enable/disable ddc1 mode. 0: disable ddc1 mode; the pin p1.3/dsda is accessed data in the ddc2b/2b+ mode. 1: enable ddc1 mode ; the pin p1.3/dsda is output data in the ddc1 mode. 3 hces h-clamp edge select. 0: pin p1.4 will output h-clamp pluse, if the leading edge of hsync occurs. 1: pin p1.4 will output h-clamp pluse, if the trailing edge of hsync occurs. 4 hcws0 h-clamp width select bit 0. 5 hcws1 h-clamp width select bit 1. 6 dummyen enable/disable dummy frequency generator. 0: disable, 1: enable. 7 adcstrt start adc conversion. 0: stop, 1: start. 3. contreg2: control register2 bit name function 0 envs enable/disable vsync separator. 0: disable, 1: enable. 1 hsps hout sync polarity select. 0: positive, 1: negative. 2 vsps vout sync polarity select. 0: positive, 1: negative. 3 - reserved.
w78c354 publication release date: october 1996 - 13 - revision a1 3. contreg2: control register2, continued bit name function 4 eintes external int edge select. 0: high-level/rising-edge triggered. 1: low-level/falling-edge triggered. 5 enm0 enable/disable sdac0 morie cancel function. 0: disable, 1: enable. 6 enm1 enable/disable sdac1 morie cancel function. 0: disable, 1: enable. 7 vdishc disable h-clamp pulse at the vsync pulse period. in initial state, it enables the h-clamp output. 0: enable, 1: disable. 4. contreg4: control register4, bit-addressable bit name function 0 p24sf enable/disable port 2.4 special function. p24sf = 0: general i/0 pin. p24sf = 1 and p2.4 = 0: sdac10 output. 1 p25sf enable/disable port 2.5 special function. p25sf = 0: general i/0 pin. p25sf = 1 and p2.5 = 0: sdac11 output. 2 p26sf enable/disable port 2.6 special function. p26sf = 0: general i/0 pin. p26sf = 1 and p2.6 = 0: sdac12 output. 3 p27sf enable/disable port 2.7 special function. p27sf = 0: general i/0 pin. p27sf = 1 and p2.7 = 0: sdac13 output. 4 p14sf enable/disable port 1.4 special function. p14sf = 0: general i/0 pin. p14sf = 1 and p1.4 = 0: h-clamp output. 5 p15sf enable/disable port 1.5 special function. p15sf = 0: general i/0 pin. p15sf = 1 and p1.5 = 0: soa output. 6 p23sf enable/disable port 2.3 special function. p23sf = 0: general i/0 pin. p23sf = 1 and p2.3 = 0: stp output. 7 invstp invert self-test pattern. note: to let the px.y output special function, set pxysf and clear px.y.
w78c354 - 14 - 5. contreg5: control register5 bit name function 0 - reserved. 1 - reserved. 2 - reserved. 3 - reserved. 4 - reserved. 5 hdsel hclamp source select. 6 dparaint enable parabola interrupt with dummy signal. dparaint = 0; v dummy signal will generate v event interrupt. dparaint = 1; v dummy signal will not generate v event interrupt. 7 - reserved. e. i/o port the i/o ports available in the w78c354 vary with the package, as shown in the table below: i/o port 68-pin plcc 48-pin dip 40-pin dip port 1 6 bits 6 bits 6 bits port 2 8 bits 8 bits 8 bits port 3 8 bits 7 bits 3 bits port 4 7 bits n.a. n.a. p1, p2, and p3 are the sfr latches of ports 1, 2, and 3, respectively. writing a "1" to a bit of a port sfr (p1, p2, or p3) causes the corresponding port output pin to switch to high. writing a "0" causes the port output pin to switch to low. when a port is used as an input, the external state of the port pin will be read into the port sfr (i.e., if the external state is low, the corresponding sfr bit will contain a "0"; if it is high, the bit will contain a "1"). the block diagrams and control registers are shown below. e-1 port 1 besides general purpose i/o functions, port 1 provides the functions shown in the following table. pins special function special function control bit description p1.0 iscl - s/w i 2 c scl pin p1.1 isda - s/w i 2 c sda pin p1.2 dscl - ddc port's scl pin p1.3 dsda - ddc port's sda pin p1.4 hclamp p14sf h-clamp pulse output p1.5 soa p15sf soa output
w78c354 publication release date: october 1996 - 15 - revision a1 cl d q q int.bus write to latch read latch read pin p1.0/p1.1 figure 2-1. p1.0/p1.1 architecture cl d q q int.bus write to latch scl output/ read latch scl input p1.2/p1.3 read pin sda output / sda input figure 2-2. p1.2/p1.3 architecture cl d q q int.bus write to latch hclamp/soa read latch read pin p1.4/p1.5 vcc internal pullup p14sf/p15sf 0 1 figure 2-3. p1.4/p1.5 architecture
w78c354 - 16 - to use the alternate function h-clamp pulse (soa output) of p1.4 (p1.5), bit p14sf (p15sf) of the sfr contreg4 must be set to "1" and a "0" must be written to p1.4 (p1.5). condition of p 14sf port 1.4 i/o pin function condition of p14sf port 1.5 i/o pin function p14sf = 0 general i/o pin p15sf = 0 general output pin p14sf = 1 & p1.4 = 0 hclamp pulse output p15sf = 1 & p1.5 = 0 soa output e-2 port 2 port 2.0 - 2.2 are used for general purpose i/o functions only, whereas 2.3 - 2.7 have alternate functions, as shown below. in the 40-pin and 48-pin dip packages, sdac10 - 13 have no dedicated output pins, but share pins with p2.4 - p2.7. each pin can be used as an i/o or sdac output pin by bit- addressing sfr contreg4. when a pin is used for a special function, the output source current is 4 ma. otherwise, the source current is 100 m a. pins special function special function control bit description p2.0 - - - p2.1 - - - p2.2 - - - p2.3 stp p23sf self -test pattern output p2.4 sdac10 p24sf sdac10 pwm output p2.5 sdac11 p25sf sdac11 pwm output p2.6 sdac12 p26sf sdac12 pwm output p2.7 sdac13 p27sf sdac13 pwm output cl d q q int.bus write to latch read latch read pin p2.0 to p2.2 vcc internal pullup figure 3-1. p2.0 to p2.2 architecture
w78c354 publication release date: october 1996 - 17 - revision a1 sdac cl d q q int.bus write to latch read latch read pin p2.n/sdac vcc internal pullup p2nsf 0 1 n+6 n+6 figure 3-2. p2.4 to p2.7 architecture (where n = 4 - 7) e-3 port 3 the architecture of port 3 is similar to that of p2.0. there are no special function control bits for these bits; the output latch of the bits must be set to high to enable the special functions. pins special function description p3.0 spid/rxd if serial port is in mode 0, the pin works as the data line of the spi port. if serial port is in mode 1, 2, or 3, the pin works as the rxd of the 80c32 standard. p3.1 spic/txd if serial port is in mode 0, the pin works as the clock line of the spi port. if serial port is in mode 1, 2, or 3, the pin works as the txd of the 80c32 standard. p3.2 int0 external interrupt input p3.3 - p3.4 t0 counter/timer 0 input p3.5 t1 counter/timer 1 input p3.6 - p3.7 -
w78c354 - 18 - e-4 port 4 port 4 is an output port. the w78c354 can write data to this port using sfr port4. cl d q q int.bus write to latch vcc internal pullup p4.0 to p4.6 figure 4-1. port 4 architecture f. spi (synchronous peripheral interface) and rs232 port p3.0 (rxd) and p3.1 (txd) can be used as an spi port (serial port mode 0 on the standard 80c32) or an rs232 port (serial port mode 1, 2, or 3 on the standard 80c32). the spi port can be used to communicate with an osd chip, dac, and so on. the rs232 port can be used to communicate with an auto-alignment system, by using a 18.432 mhz crystal. maximum baud rate is 19200 bps. g. ddc port (display data channel port) the ddc port is composed of the sio1 and ddc1 ports, and the sio1 port shares the dsda pin with the ddc1 port (as shown in figure 5). the ddc port is designed to support ddc1, ddc2b, and ddc2b+ applications. g-1 sio1 port sio1 is an i 2 c serial i/o port. sio1 provides a serial interface that meets the i 2 c bus specification and supports all transfer modes from and to the i 2 c bus. the sio1 port handles byte transfers autonomously. the w78c354 interfaces to the sio1 port through the following four special function registers: s1con (sio1 control register), s1sta (sio1 status register), s1dat (sio1 data register), and s1adr (sio1 address register). the sio1 port interfaces to the ddc i 2 c bus via two pins: p1.2 / dscl (ddc i 2 c serial clock line) and p1.3/dsda (ddc i 2 c serial data line). the output latches of p1.2 and p1.3 must be set to "1" in order to enable the sio1 port. for more detailed information, refer to the description of the philips i 2 c bus. g-1.1 s1adr (sio1 address register) (dah) the w78c354 can read from and write to this 8-bit newly added sfr s1adr. when the the sio1 port is in a master mode, the content of this register is irrelevant. in slave mode, the seven most significant bits must be loaded with the address that owns the slave.
w78c354 publication release date: october 1996 - 19 - revision a1 7 6 5 4 3 2 1 0 s1adr x x x x x x x - |--------------- address that owns slave ---------------| g-1.2 s1dat (sio1 data register) (dbh) this register contains a byte of serial data that is waiting to be transmitted or has just been received. when the w78c354 is not performing a shifting operation, data can be read from or written to sfr s1dat. data in the s1dat remain stable as long as si is set. data in the s1dat are shifted from the most significant bit to the least significant bit, and while data are being shifted out, data on the bus are simultaneously being shifted in. s1dat always contains the last data byte present on the bus. thus, if arbitration is lost, the transition from master transmitter to slave receiver is made with the correct data in s1dat. 7 6 5 4 3 2 1 0 s1dat sd7 sd6 sd5 sd4 sd3 sd2 sd1 sd0 msb lsb eight bits of data in the s1dat are shifted out or in, followed by an acknowledge bit. the acknowledge (ack) bit is controlled by the sio1 port hardware and cannot be accessed by the w78c354. serial data are shifted through the ack flag into s1dat on the rising edges of the serial clock pulses on the scl line and are shifted out from the s1dat on the falling edges of the scl clock pulse. when a byte has been shifted into the s1dat, the serial data are available in s1dat, and the acknowledge bit is returned by the control logic during the ninth clock pulse. g-1.3 s1con (sio1 control register) (d8h) the newly added sfr s1con can be read or written by the programmer. two bits (si and sto) are affected by the sio1 port hardware. when a serial interrupt is requested, the bit si is automatically set, and when a stop condition is present on the bus, the bit sto is cleared. the bit sto is also cleared when ens1 = "0." 7 6 5 4 3 2 1 0 s1con cr2 ens1 sta sto si aa cr1 cr0 g-1.4 ens1 (sio1 enable bit) when the bit ens1 is "0," the sda and scl outputs are in a high impedance state, the sio1 port is in the "not addressed" slave mode, and no other bits are affected, except that the bit sto in s1con is forced to "0." p1.2 and p1.3 may be used as open drain i/o pins. when ens1 is "1," sio1 is enabled. the p1.2 and p1.3 pins must be set to high.
w78c354 - 20 - g-1.5 sta (sio1 start flag) when sta is "1," the sio port will enter the master mode. after the sio1 port checks the status of the i 2 c bus, it will generate a start condition if the bus is free. if the bus is not free, the sio1 port will wait for a stop condition and then generate a start condition after a delay. if the bit sta is set while sio1 is already in master mode and one or more bytes are to be transmitted or received, sio1 will transmit a repeated start condition. the bit sta may also be set when sio1 is an addressed slave. when sta is "0," no start condition or repeated start condition will be generated. g-1.6 sto (sio1 stop flag) when sto is "1," the sio1 port is in the master mode and a stop condition is transmitted to the i 2 c bus. when the stop condition is detected on the bus, the sio1 port will clear sto. in the slave mode, sto may be set to recover from an error condition. in this case, no stop condition exists the i 2 c bus, but the sio1 port behaves as if a stop condition has been received and switches to the defined "not addressed" slave receiver mode. sto is automatically cleared by hardware. g-1.7 si (sio1 serial interrupt flag) when si is "1," if the bits ea and es1 (in the ie register) are also set, then once a serial interrupt is requested, si will automatically be set by hardware. the only state that does not cause si to be set is state f8h, which indicates that no relevant state information is available. when the bit si is "1," the low period of the serial clock on the scl pin is extended, and the serial transfer is suspended. si must be reset by software. when si is "0," no serial interrupt is requested, so there is no extension of the serial clock on the scl pin. g-1.8 aa (sio1 assert acknowledge flag) if aa is "1," an acknowledge signal (low level to the sda pin) will be generated during the acknowledge clock pulse on the scl pin when: (1) the address owning the slave has been received. (2) a data byte has been received while the sio1 port is in the master receiver mode. (3) a data byte has been received while the sio1 port is in the addressed slave receiver mode. if the bit aa is "0," a not acknowledge signal (high level to the sda pin) will be generated during the acknowledge clock pulse on the scl pin when: (1) a data byte has been received while the sio1 port is in the master receiver mode (2) a data byte has been received while the sio1 port is in the addressed slave receiver mode. g-1.9 cr0, cr1 and cr2 (sio1 clock rate bits) when the sio1 port is in master mode, these three bits will determine the serial clock frequency (see the table below). these bits are unimportant when sio1 is in slave mode. in slave mode, the sio1 port will automatically synchronize with any clock frequency up to 100 khz on the i 2 c bus.
w78c354 publication release date: october 1996 - 21 - revision a1 table 3. serial clock rates bit frequency (kh z ) at the scl pin cr2 cr1 cr0 16 mh z 18.432 mh z 20 mh z formula 0 0 0 63 72 78 f osc /256 0 0 1 71 82 89 f osc /224 0 1 0 83 96 - f osc /192 0 1 1 100 - - f osc /160 1 0 0 17 19 20 f osc /960 1 0 1 - - - f osc /120 1 1 0 - - - f osc /60 g-1.10 s1sta (sio1 status register) (d9h) the newly added sfr s1sta is an 8-bit read-only register. the three least significant bits are always zero. the five most significant bits contain the status code. there are 26 possibile status codes. when the s1sta contains f8h, no serial interrupt is requested. all other the s1sta values correspond to defined sio1 states (refer to the philips specification for the i 2 c bus). when each of these states is entered, a status interrupt is requested (si = 1). a valid status code is present in the s1sta one machine cycle after the bit si is set by hardware and is still present one machine cycle after the bit si has been reset by software. g-2 ddc1 port ddc1 is a serial output port that supports ddc1 communication. after the ddc1 control circuit loads the next data byte from the data buffer to the shift register and generates a ddc1int signal to the cpu, eight data bits and one zero (for the "acknowledge" signal) are shifted out to the dsda pin sequentially on each rising edge of the vin signal. in the interrupt service routine, the w78c354 should fetch the next byte of edid data and write it to sfr ddc1. if the bit enddc1 of sfr contreg1 is cleared to zero, the shift register is stopped, and the dsda output is kept high. one ddc1 port to support ddc1; enddc1 must be set to 1. one sio1 port support ddc2b/2b+; enddc1 must be set to 0.
w78c354 - 22 - ddc1 port enddc1 p1.2/dscl p1.3/dsda sio1 port support ddc2b/2b+ support ddc1 scl sda sda scl 0 1 v sda in scl in out in out figure 5. ddc port h. interrupts the w78c354 has six interrupt sources. five (except int1 , at vector address 0013h) are identical to those in the 80c51 series, while the sixth (at vector address 002bh) is newly added. all the interrupt sources and the corresponding interrupt vector addresses for the w78c354 are described in the following table: source vector address description priority ie0 0003h external interrupt 0 (same as the 80c31) highest tf0 000bh timer 0 overflow interrupt (same as the 80c31) *1 0013h replaces int1 of the 80c31 tf1 001bh timer 1 overflow interrupt (same as the 80c31) ri+ti 0023h serial port interrupt (same as the 80c31) *2 002bh new (similar to tf2+exf2 in the 80c32) lowest notes: *1. dsclint+adcint+timeout+soaint+vevent+paraint+ddc1int. *2. this is the interrupt generated by the i 2 c in the ddc port.
w78c354 publication release date: october 1996 - 23 - revision a1 h-1. interrupt at vector address 0013h the interrupt at vector address 0013h is driven by another seven different sources, which are a high- to-low transition on the dscl pin of the ddc port, the a/d converter, the auto-reload timer, the soa output, vsync frequencg event, the parabola interrupt generator, and ddc1 in the ddc port. these sources are described below. (1) dsclint: interrupt generated when dscl-pin changes from high to low and stays high for 12 clock periods. once ddclint interrupt is received, the programmer should disable ddc1 port by writing "0" to the bit enddc1 of sfr contreg1. 16 mh z 18.432 mh z 20 mh z dscl low 750 ns 651 ns 600 ns (2) adcint: refer to section k for a description of the adc. (3) timeout: refer to section i for a description of the auto-reload timer. (4) soaint: when an soa condition occurs, soaint will interrupt the cpu to perform the necessary operations. refer to section m-6 for a description of the soa function. (5) vevent: when the v retrace signal is detected or the v-frequency counter overflows, which means that the vsync frequency is so low that it is out of range, the w78c354 will generate the vevent interrupt. in the interrupt service routine, the programmer can check bit 3 (nov) of sfr status to determine whether the v frequency is out of range. if nov = 1, the software should go to dpms process. if nov = 0, the software can read the hfcount and vfcount registers, and the bits hp and vp of status will determine the preset mode of the incoming frequency. refer to section m for a description of the sync processor. (6) paraint: the parabola interrupt generator is used to generate interrupts to the w78c354 for loading the parabola waveform data to dynamic dacs. the software should calculate the value of the parah and paral registers by (vcount 16) ? section number. refer to section j for a description of the parabola interrupt generator. (7) ddc1int: refer to section g-2 for a description of the ddc1 operation. programmer must read sfr intvect (bits 0 - 6) to determine the source of the interrupt request. these seven interrupt sources can be enabled individually by setting sfr intmsk (bits 0 - 6). the newly added interrupt at vector address 002bh is driven by the i 2 c circuit in the ddc port. the interrupt enable control bits for the two interrupts at 0013h and 002bh are ie.2 and ie.5 in the ie register, respectively. the interrupt priority control bits are ip.2 and ip.5 in the ip register. the interrupts can be disabled by clearing ie.7 (disable all interrupts). for example, the programmer can enable the a/d converter interrupt by the "mov intmsk, #00000010b" instruction. when the
w78c354 - 24 - converter is completed, the interrupt will be generated and the bit adcint in the intvect will automatically be set. to clear the bit adcint to receive the next interrupt, the programmer can use the "mov intvect, #00000010b" instruction. see figure 6. i c in ddc port 2 or timeout source dsclint source adcint source paraint source vevent source ddc1int source ie0 tf0 tf1 ri+ti intmsk ie 0013h 001bh 0023h 002bh 000bh 0003h ie.3 ie.4 ie.5 ie.2 ie.1 ie.0 ie.7 ip ip.0 ip.1 ip.2 ip.3 ip.4 ip.5 vector address high priority low priority interrupt polling sequence soaint source timeout dsclint adcint paraint vevent ddc1int soaint intvect bit 0 bit 1 bit 2 bit 4 bit 3 bit 6 bit 5 figure 6. interrupt block diagram h-2. newly added external interrupt 0 function (int0) int0 can be set to be falling-edge or low-level active by setting/clearing the it0 bit in tcon. if programmers wish to use a rising-edge or high-level signal as interrupt on the pin int0, int0 can also be activated by setting/clearing the eintes bit in sfr contreg2 (see figure 7). in other words, there are four trigger types for int0 (falling-edge, low-level, rising-edge. and high-level). in the initial state, int0 will be triggered by a rising-edge or high-level signal. 0 1 eintes ie0 it0 1 int0 (p3.2) 0 figure 7. external interrupt 0
w78c354 publication release date: october 1996 - 25 - revision a1 intvect : interrupt vector register (b2h) bit name function 0 dsclint set by hardware when dscl is toggled low. 1 adcint set by hardware when adc conversion is completed. 2 timeout set by hardware when autoload timer times out. 3 soaint set by hardware when soa is high. 4 vevent set by hardware when vsync or vertical frequency counter times out. 5 paraint set by hardware when parabola interrupt generator times out. 6 ddc1int set by hardwrae when ddc port functions in the ddc1 mode . 7 - reserved. notes: 1. each of the above interrupt flags will be set by hardware when the corresponding interrupt source is masked by writing a "1" to the the intmsk register. 2. to clear the interrupt flag, write a "1" (not "0") to the corresponding bit. intmsk : interrupt mask register (95h) bit name function 0 dsclint enable/disable dsclint interrupt. 0: disable, 1: enable. 1 adcint enable/disable adcint interrupt. 0: disable, 1: enable. 2 timeout enable/disable timeout interrupt. 0: disable, 1: enable. 3 soaint enable/disable soaint interrupt. 0: disable, 1: enable. 4 vevent enable/disable vevent interrupt. 0: disable, 1: enable. 5 paraint enable/disable paraint interrupt. 0: disable, 1: enable. 6 ddc1int enable/disable ddc1int interrupt. 0: disable, 1: enable. 7 - reserved
w78c354 - 26 - i. timer/counter the w78c354 has two 16-bit timer/counters, timer/counter 0 and timer/counter 1, which are identical with those on the standard 80c32, and one 8-bit auto-reload timer. once the "mov autoload, #data" instruction is executed, the auto-reload timer will load the specified data and start to count. if the timeout bit in intmsk is set, the auto-reload timer will periodically generate an interrupt to the cpu. the auto-reload timer interval is programmable: minimum timer interval = 1/(f clock ? 1024) desired timer interval = minimum interval [(preset value of the autoload)+1] maximum timer interval = minimum interval 255 autoload: 8-bit auto-reload timer register which stores preset value. 16 mh z 18.432 mh z 20 mh z minimum interval 64 m s 55 m s 51.2 m s maximum interval 16.3 m s 14.2 m s 13.1 m s j. parabola interrupt generator the parabola interrupt generator is a 16-bit binary count-up auto-reload timer that is used to generate the parabola interrupt to the w78c354 for loading parabola waveform data to dynamic dacs. it periodically generates an interrupt by setting the paraint bit in intmsk, if the "mov paral, #low byte data" and "mov parah, #high byte data" instructions are executed. the parabola interrupt generator period is programmable: time base = 1/f clock desired interrupt period = time base {[preset value of the (parah, paral)]+1} maximum period = time base 65535 paral: parabola interrupt generator register that stores low byte preset value parah: parabola interrupt generator register that stores high byte preset value k. 6-bit a/d converter the 6-bit analog-to-digital converter uses the successive approximation method to convert one of the four analog input channels into a digital data value. the a/d converter resolution is 1 lsb, and the conversion time is 100 usec. the result is read from sfr adc. bit-pairs (adcs1, adcs2) in sfr contreg1 are used to select one of the four channels as the analog input (see table 3). conversion is started by setting the bit adcstrt in contreg1 by software. when the a/d conversion is completed, the adcstrt bit is automatically cleared by hardware to stop the a/d converter's operation, and the adcint bit in intvect is set by hardware at the same time. to enable the a/d converter interrupt, set the adcint bit in intmsk. table 4. select a/d converter channel (adcs1, adcs0) (0, 0) (0, 1) (1, 0) (1, 1) selected channel adc0 adc1 adc2 adc3
w78c354 publication release date: october 1996 - 27 - revision a1 l. pwm dacs there are two 12-bit and fourteen 8-bit pwm static dacs and one 12-bit and three 8-bit pwm dynamic dacs on this chip. the number of the pwm outputs is different with the package. 68-pin plcc 48-pin dip 40-pin dip 8-bit sdac 14 8 + 4* 8 + 4* 12-bit sdac 2 1 1 8-bit ddac 3 3 1 12-bit ddac 1 1 1 note : 4* : the sdac s share with p2.4~p2.7 l-1.1 14-channel 8-bit pwm static dac the static dacs (sdac0 to 13) are used to generate dc voltage control (0 to 5v) by an rc circuit, as shown in figure 8, and to execute the "mov sdacn, #value" instruction. there are 14 registers, corresponding to the 14 channels of 8-bit pwm output. the unused pwm channel can be used as an output pin, since 0 or 5v can be obtained from the pin. duty cycle of the pwm output = preset value of sdacn ? 255, where n = 0 to 13 dc voltage after low-pass filter = v cc duty cycle sdac0 - sdac13: 8-bit pwm static dac registers storing preset values preset value duty cycle dc voltage 0 0/255 0v 1 1/255 1/255 5v n n/255 n/255 5v 255 255/255 +5v pwm frequency f pwm = f clock ? 255 fclock 16 mhz 18.432 mhz 20 mhz f pwm 62.745 khz 72.282 khz 78.431 khz t pwm 15.94 m s 13.83 m s 12.75 m s
w78c354 - 28 - 8/12bit sdac low-pass filter v output r c w78c354 figure 8. sdac application circuit (where t = rc, v output = v cc n/255, if t >> t pwm ) when bit enm0 of sfr contreg2 is set to high, sdac0 will output pwm in one frame and then keep low for the next frame. thus sdac0 can be used for h moire cancellation. sdac1 can also be configured with the same operation for v moire cancellation by setting bit enm1. the application circuit is shown below. sdac0 (h-moire) sdacx (h-phase) h-phase control circuit figure 9. moire application circuit l-1.2 two-channel 12-bit pwm/brm static dac the two 12-bit pwm/brm outputs (bsdac0,1) are composed of an 8-bit pwm and a 4-bit brm (bit rate multiplier). the value of the 4-bit brms (sfrs sbrm0, 1) determine to which positions one clock pulse will be added in every 16 pwm outputs of 12-bit pwm/brm static dac0,1. when the "mov bsdacn, #value" or "mov sbrmn, #value" instruction is executed, the related output pin will output the pwm waveform needed by the user. the 12-bit pwm/brm frequency is the same as that of the 8-bit pwm output. value of sbrm0 or sbrm1 (bit3 bit2 bit1 bit0) one clock pluse incremented in the n-th output every 16 pwm outputs 0000 none 0001 n = 8 0010 n = 4, 12 0100 n = 2, 6, 10, 14 1000 n = 1, 3, 5, 7, 9, 11, 13, 15
w78c354 publication release date: october 1996 - 29 - revision a1 in the following table, in the positions marked with an " " one clock pulse will be added to every 16 pwm outputs. sbrm0, pwm/brm output cycle sbrm1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0000 - - - - - - - - - - - - - - - - 0001 - - - - - - - - - - - - - - - 0010 - - - - - - - - - - - - - - 0011 - - - - - - - - - - - - - 0100 - - - - - - - - - - - - 0101 - - - - - - - - - - - 0110 - - - - - - - - - - 0111 - - - - - - - - - 1000 - - - - - - - - 1001 - - - - - - - 1010 - - - - - - 1011 - - - - - 1100 - - - - 1101 - - - 1110 - - 1111 - l-2. three-channel 8-bit and one-channel 12-bit pwm dynamic dacs the 8-bit pwm dynamic dacs (ddac0-2) and 12-bit pwm dynamic dac (bddac) are used to achieve geometric compensation by generating a parabola output waveform by the integrator circuit shown in figure 6 and by executing the "mov ddacn, #value," "mov bddac, #value," or "mov dbrm, #value" instructions by a software program. the pwm waveforms and operating criteria of the related registers are similar to those of the static dacs. the unused dynamic dacs can be used as static dacs. w78c354 8/12 bit ddac 2.5 v v output r c figure 10. dynamic dac application circuit
w78c354 - 30 - the objective of the dynamic dac is to generate geometric compensation parabola waveforms. several examples are given below. l-3. examples l-3.1 ddac0 used to compensate for h size distortion 1. pincushion (pcc amplitude) 2. trapezoid (keystone) 3. cbow (s-comp) 25% 25% 4. pcc corner l-3.2 ddac1 used to compensate for h center distortion 1. pin balance (bow) 2. key balance (tilt) m. sync processor the sync processor is composed of a polarity detector, sync separator, h/v frequency counter, h/v dummy frequency generator, h-clamp generator, and soa generator. figure 11 is a block diagram of the sync processor. the related control bits are defined in sfr contreg2. the sync processor supports powerful functions that enable users to employ the v/h , h-clamp, and soa outputs to easily control and protect the deflection circuit.
w78c354 publication release date: october 1996 - 31 - revision a1 h / v a d [ 7 : 0 ] 1 0 0 0 0 0 1 1 1 1 vsps hsps dummyen envs vin hin vdishc frequency counter polarity detect & restoration vrest hrest sync separator vsep vdummy hdummy h/v dummy sync generator vout hout h - clamp soa h-clamp generator soa generator figure 11. sync processor m-1. polarity detector the h/v polarity is detected automatically and can be read from sfr status. the polarity of the h/v input signals is then restored (they signals become hrest/vrest) for internal processing and output to hout/vout to drive the deflection circuit. maximum sync width to hin pin: (1/f clock ) 2 14 maximum sync width to vin pin: (1/f clock ) 2 14 fclock 16 mh z 18.432 mh z 20 mh z max. sync width for hin 1024 m s 888 m s 819 m s max. sync width for v in 1024 m s 888 m s 819 m s m-2. sync separator vsync is separated from the composite sync automatically, without any additional software programming. figure 12 shows the waveforms of v out that result from a composite or non-composite hsync input. if envs = 1, the limitations on the vsync signal are: v in pulse width must be larger than wvmin = [(1/f clock ) ?? 128.5] 1/(2 f clock ) v out is delayed from v in signal by tdelay = [(1/f clock ) ?? 128.5] 1/(2 f clock )
w78c354 - 32 - f clock 16 mh z 18.432 mh z 20 mh z 1/fclock 62.5 n s 54 n s 50 n s min. vsync width (wvmin) 8031 31 n s 6939 27 n s 6425 25 n s v out delay from v in (tdelay) 8031 31 n s 6939 27 n s 6425 25 n s h vmin 1. withot composite sync h v v 2. with composite sync delay t w h in v in h out v out in (h+v) in out out figure 12. vsync separator output (when dummyen = 0, envs = 1) m-3. horizontal & vertical frequency counter there are two 16-bit counters that automatically count the horizontal and vertical frequency. when a vevent interrupt occurs, the w78c354 reads the count value (h count and v count ) from the 8-bit counter registers (hfcounth, hfcountl, vfcounth, and vfcountl) to calculate the h and v frequency by the formulas listed below.
w78c354 publication release date: october 1996 - 33 - revision a1 v frequency: resolution of v frequency counter: v resol = (1/f clock ) 16 v-frequency: v freq = 1/(v count v resol ) lowest v frequency can be detected: f clock ? 1048576 h frequency: resolution of h frequency counter: h resol = (1/f clock ) ? 8 h-frequency: h freq = 1/(h count h resol ) lowest h frequency can be detected: f clock ? 8192 16 mh z 18.432 mh z 20 mh z vresol 1 m s 868 n s 800 n s lowest v freq 15 hz 17.6 hz 19 hz hresol 7.8 n s 6.8 n s 6.3 n s lowest h freq 1.9 khz 2.3 khz 2.4 khz m-4. dummy frequency generator the dummy h and v frequencies are generated for factory burn-in measurement and for displaying a warning message when there is no input h/v frequency. the dummy sync generator includes two newly added sfrs, dhreg and dvreg. dhreg is a 4-bit register used to determine the dummy hsync output frequency. dvreg is an 8-bit register that can be used to preset a constant into dvreg to determine the dummy vsync output frequency by the formulas listed below. dummy hsync frequency f dh = f clock ? 32 ? (dhreg+1) dummy vsync frequency f dv = f dh ? 8 ? (dvreg+1) example: assume system clock = 16 mhz dhreg f dh dvreg f dv 15 31.25k 48 79.7 hz 12 38.5k 59 80.2 hz 10 45.5k 70 80.1 hz 9 50k 77 80.1 hz 7 62.5k 96 80.5 hz 5 82k 127 80.1 hz 4 100k 155 80.1 hz
w78c354 - 34 - the relations between the bit dummyen and the outputs of the h/v frequencies are listed below: hout vout dummyen = 0 hrest vrest (if envs = 0) vsep (if envs = 1) dummyen = 1 h dummy v dummy m-5. h-clamp pulse generator if the p14sf bit is set in the newly added sfr contreg4 (bit-addressable), the output pin p1.4 can be used as the h-clamp pulse output (refer to figure 13). the hsync trigger type can be selected to generate the h-clamp output pulse, and the pulse width of the h-clamp output can be determined by programming the bits hces, hcws1, and hcws2 in sfr contreg1. for details, see the following figure and description. condition o f p14sf port 1.4 i/o pin function p14sf = 0 general i/o pin p14sf = 1 & p1.4 = 0 h-clamp pulse output 0 1 p14sf p1.4/hclamp p1.4 output latch h-clamp pulse figure 13. alternate function of p1.4 1. select the leading edge or trailing edge of hsync: hces = 0: select leading edge hces = 1: select trailing edge
w78c354 publication release date: october 1996 - 35 - revision a1 hsync hsync (a) negative polarity hsync (b) postive polarity hsync (leading-edge) (trailing-edge) p1.4 p1.4 (leading-edge) (trailing-edge) p1.4 p1.4 figure 14. pin p1.4 outputs the h-clamp pulse at the leading edge or trailing edge of hsync. 2. pulse width of h-clamp pulse: select the weighting of h-clamp pulse by programming bits hcws0 and hcws1 in contreg1 pulse width of h-clamp output: [(1/f clock ) weighting] [ 1/(2 f clock )] (hcws1, hcws0) weighting 16 mh z 18.432 mh z 20 mh z (0, 0) 4.5 281 31 n s 244 27 n s 225 25 n s (0, 1) 8.5 531 31 n s 461 27 n s 425 25 n s (1, 0) 16.5 1031 31 n s 896 27 n s 825 25 n s (1, 1) 32.5 2031 31 n s 1764 27 n s 1625 25 n s hsync h-clamp output figure 15. pulse width of h-clamp output
w78c354 - 36 - if the bit vdishc of sfr contreg2 is set high, the h-clamp pulse output will be disabled in the v sync pulse period. vdishc v h h-clamp in in figure 16. disable h-clamp output m-6. safe operation area (soa) output the purpose of the soa output is to protect the hot (horizontal oscillating transistor) and other critical circuitry by responding quickly if the hsync frequency suddenly drops below a preset boundary frequency. when the hsync frequency is lower than the preset boundary frequency for three consecutive cycles or stops for a certain period, the soa pin (p1.5) will change to a "high" state to activate an external circuit to protect the monitor. if the bit p15sf is set in sfr contreg4, the pin p1.5 can be used as the soa output (refer to figure 17). the soa pin can be released by writing any value to sfr soaclr. condition o f p15sf port 1.5 i/o pin function p15sf = 0 general i/o pin p15sf = 1 & p1.5 = 0 soa output 0 1 p15sf p1.5/soa p1.5 output latch soa output figure 17. alternate function of p1.5 boundary frequency h boun d = 2 mhz ? (value of soareg) example: if 50 khz is considered the boundary frequency, then value of soareg = 2m ? 50k = 40. no hsync response time = 2048 (1/f clock ).
w78c354 publication release date: october 1996 - 37 - revision a1 16 mh z 18.432 mh z 20 mh z no hsync response time 128 m s 11 1 m s 102 m s m-7. self-test pattern output when the dummy frequency generator is enabled, if bit p23sf of sfr contreg4 is set, the stp output will provide a checkerboard pattern for burn-in or self-diagnostic purposes. the bit invstp of contreg4 can invert the checkerboard pattern to avoid phosphor damage during factory burn-in. condition o f p23sf port 2.3 i/o pin function p23sf = 0 general i/o pin p23sf = 1 & p2.3 = 0 stp output 0 1 p23sf p2.3/stp p2.3 output latch stp output figure 18. alternate function of p2.3 invstp = 0 invstp = 1 figure 19. checkerboard pattern
w78c354 - 38 - n. power supervisor, watchdog timer, and reset circuitry reset signals can come from three sources: an external reset input (active low), power-low detection, or the watchdog timer. figure 20 is a block diagram of the reset circuitry. the power-low detection circuit generates a reset signal if v cc falls below 3.8v, and the reset signal will keep twenty-four machine cycle after v cc rises to 4.3v. thus we can make sure the chip can be reseted perfectly when the monitor is first powered on, and avoid the w78c354's overwriting the e 2 prom mistakenly when the monitor is powered down. the power-low detection circuit can be enabled or disabled by code option 1. the purpose of the watchdog timer is to reset the w78c354 if it enters an abnormal processor state (caused by electrical noise or rfi, for example). the clock source of the watchdog timer comes from the internal system clock. the timer can be enabled or disabled by the code option 2. when enabled, the watchdog circuitry will generate a system reset if the user's program fails to reload the watchdog timer within a specified length of time after executing the "mov wdtclr, # value" instruction. this length of time is known as the "watchdog interval" (t wdt ). four selections are available for the watchdog interval (type a, b, c, and d); the selections, which are programmed by code option 3, are indicated by the formulas in table below. there are three code options in the reset circuitry: code option 1: enable/disable the power-low detector. code option 2: enable/disable the watchdog timer. code option 3: select one watchdog interval (type a, b, c, d as listed in the table below.) watchdog timer power-low detector enable/disable external reset system reset code option 2 code option 1 enable/disable code option 3 watchdog interval figure 20. reset circuitry
w78c354 publication release date: october 1996 - 39 - revision a1 table4. watchdog interval t wdt f clock code option 3 formula 16 mh z 18.432 mh z 20 mh z type-a 2 19 /f clock 32 m s 28 m s 26 m s type-b 2 21 /f clock 131 m s 113 m s 104 m s type-c 2 23 /f clock 524 m s 452 m s 417 m s type-d 2 24 /f clock 1048 m s 905 m s 834 m s absolute maximum ratings parameter symbol min. max. unit dc power supply v cc - v ss - 0.3 +7.0 v input voltage v in v ss - 0.3 v cc +0.3 v operating temperature t a 0 70 c storage temperature t st -55 +150 c note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the device. dc electrical characteristics v cc - v ss = 5v 10%, t a = 25 c, f osc = 20 mhz, unless otherwise specified parameter sym. conditions min. typ . max. unit operating voltage v dd 4.5 5 5.5 v operating current i dd no load, v dd = 5.5v - - 65 ma idle current i idle idle mode, v dd = 5.5v - - 30 ma logic 0 input current p1, p2, p3 (except p1.0 to p1.3 ,p1.5) i in1 v dd = 5.5v v in = 0v -75 - -10 m a input current reset [*1] i in2 v dd = 5.5v v in = 0v -250 - - m a input current hin, vin [*2] i in3 v dd = 5.5v v in = v dd - - + 30 m a input leakage current p1.0 to p1.3, adc0 to adc3 i lk v dd = 5.5v 0v < v in < v dd -10 - +10 m a
w78c354 - 40 - dc electrical characteristics, continued parameter sym. conditions min. typ. max. unit logical 1-to-0 transition current p1, p2, p3 [*3] (except p1.0 to p1.3, p1.5) i tl v dd = 5.5v v in = 2.0v -650 - - m a input low voltage reset , oscin [*4] (except p1.0 to p1.3, p1.5) v il1 v dd = 4.5v 0 - 0.8 v input low voltage hin, vin [*5] v il2 v dd = 4.5v 0 - 0.8 v input low voltage p1.0 to p1.3 v il3 v dd = 4.5v 0 - 1.5 v input high voltage p1, p2, p3 (except p1.0 to p1.3, p1.5) v ih1 v dd = 5.5v 2.4 - v dd +0.2 v input high voltage reset , oscin [*4] v ih2 v dd = 5.5v 3.5 - v dd +0.2 v input high voltage hin, vin [*5] v ih3 v dd = 5.5v 2.4 - v dd +0.2 v input high voltage p1.0 to p1.3 v ih4 v dd = 5.5v 3.0 - v dd +0.2 v output low voltage p1 .4 , p 1.5 , p 2.2 to p2.7 sdac0 to sdac13 h out , v out v ol1 v dd = 4.5v i ol = +4 ma - - 0.45 v output low voltage p1.0, p1.1 v ol2 v dd = 4.5v i ol = + 2 ma - - 0.4 v output low voltage p1.2, p1.3 v ol3 v dd = 4.5v i ol = + 6 ma - - 0.4 v output low voltage p2.0, p2.1 v ol4 v dd = 4.5v i ol = +15 ma - - 0.45 v output low voltage p3, p4 v ol5 v dd = 4.5v i ol = + 2 ma - - 0.45 v
w78c354 publication release date: october 1996 - 41 - revision a1 dc electrical characteristics, continued parameter sym. conditions min. typ. max. unit output low voltage bsdac0-1 , ddac0-2, bddac v ol6 v dd = 4.5v i ol = +8 ma - - 0.45 v output high voltage p1 .4 , p2, p3 v oh1 v dd = 4.5v i oh = -100 m a 2.4 - - v output high voltage p1.5, sdac0-13, h out , v out , special function of p1.4 and p2.3~ p2.7 v oh2 v dd = 4.5v i oh = -4 ma 2.4 - - v output high voltage , bsdac0-1 , ddac0-2, bddac v oh3 v dd = 4.5v i oh = -8 ma 2.4 - - v output high voltage p4 voh4 v dd = 4.5v i oh = -2ma 2.4 - - v notes: 1. the reset pin has an internal pull-up resistor with a resistance of about 30 k w . 2. pins hin and vin have an internal pull-down resistor with a resistance of about 200 k w . 3. pins p1, p2, and p3 (except p1.0-p1.3 and p1.5) source a transition current when they are being externally driven from 1 to 0. the transition current reaches its maximum value when v in is approximately 2v. 4. reset is a schmitt trigger input, and oscin is a cmos input. 5. hin and v in are schmitt trigger inputs.
w78c354 - 42 - typical application circuit h-size v-size h-phase v-center sdac0 sdac1 sdac2 sdac3 sda scl p2.0 p2.1 hflb vflb osd mc141540 ss hout vout p2.2 sdac4 sdac5 sdac6 sdac7 p2.4/sdac10 p2.5/sdac11 p2.6/sdac12 p2.7/sdac13 brightness contrast rotation r-gain b-gain r-cut off b-cut off g-cut off cs0 mute degauss power saving trap\cbow\pin tilt\bow bddac ddac0 p3.3 p3.4 p3.5 p4.0 vdd oscout oscin 30p 30p 16m p4.1 p4.2 p1.4 p1.5 p2.3 cs1 cs2 soa output h-clamp output stp output auto alignment p3.0/rxd p3.1/txd a d c 0 / r s t hin vin p1.3/dsda p1.2/dscl 24c04 10k vdd r1 r2 r3 vdd s0 s1 s2 r4 10uf r5 s3 scl sda r6 r7 p1.1/isda p1.0/iscl e prom 2 vga w78c354 r8 vdd r9
w78c354 publication release date: october 1996 - 43 - revision a1 package dimensions 68-pin plcc 68 61 60 44 43 27 26 10 9 1 l c 1 b 2 a h d d e b e h e y a a 1 seating plane d g g e notes: symbol min. nom. max. max. nom. min. dimension in inches dimension in mm a b c d e h e l y a a 1 2 e b 1 h d g g d e on final visual inspection spec. 4. general appearance spec. should be based 3. controlling dimension: inches protrusion/intrusion. 2. dimension b1 does not include dambar flash. 1. dimensions d & e do not include interlead 0.020 0.143 0.026 0.016 0.006 0.949 0.895 0.980 0.090 0.148 0.028 0.018 0.008 0.954 0.915 0.990 0.100 0.050 0.185 0.153 0.032 0.022 0.012 0.959 0.935 1.000 0.110 0.004 0.51 3.63 0.66 0.41 0.15 24.10 22.73 24.90 2.29 3.76 0.71 0.46 0.20 24.23 23.24 25.15 2.54 1.27 4.70 3.89 0.81 0.56 0.30 24.36 23.75 25.40 2.79 0.10 10 0 0 10 0.044 0.056 1.12 1.42 24.36 24.23 24.10 0.959 0.954 0.949 23.75 23.24 22.73 0.935 0.915 0.895 25.40 25.15 24.90 1.000 0.990 0.980 q q 48-pin dip max. nom. min. dimension in inches dimension in mm a b c d e a l s a a 1 2 e b 1 1 e e 1 a 15 e seating plane base plane b b e 1 1 s d e a l 1 c a 1 e a a 48 1 25 24 a 2 notes: 1. dimensions d max. & s include mold flash or the bar burrs. 2. dimension e1 does not include interlead flash. 3. dimensions d & e1 include mold mismatch and are determined at the mold parting line. 4. dimension b1 does not include dambar protrusion/intrusion. 5. controlling dimension: inches. 6. general appearance spec. should be based on final visual inspection spec. min. nom. max. symbol 0 15 0 0.63 0.65 0.67 16.0 16.5 17.0 0.08 2.1 0.12 0.13 0.14 3.0 3.3 3.5 0.55 0.54 0.11 0.55 0.10 0.09 2.2 2.5 2.7 13.8 13.9 14.1 0.60 0.59 0.61 14.9 15.2 15.4 2.45 2.46 62.2 62.4 0.01 0.00 0.01 0.2 0.2 0.3 0.05 0.04 0.05 0.01 0.01 0.02 0.15 0.15 0.16 0.01 0.21 1.2 1.2 1.3 0.4 0.4 0.5 3.8 3.9 4.0 0.2 5.3
w78c354 - 44 - 40-pin dip seating plane 1. dimensions d max. & s include mold flash or tie bar burrs. 2. dimension e1 does not include interlead flash. 3. dimensions d & e1 include mold mismatch and are determined at the mold parting line. 6. general appearance spec. should be based on final visual inspection spec. . 1.372 1.219 0.054 0.048 notes: symbol min. nom. max. max. nom. min. dimension in inches dimension in mm a b c d e a l s a a 1 2 e 0.050 1.27 0.210 5.334 0.010 0.150 0.016 0.155 0.018 0.160 0.022 3.81 0.406 0.254 3.937 0.457 4.064 0.559 0.008 0.120 0.670 0.010 0.130 0.014 0.140 0.203 3.048 0.254 3.302 0.356 3.556 0.540 0.550 0.545 13.72 13.97 13.84 17.01 15.24 14.986 15.494 0.600 0.590 0.610 2.286 2.54 2.794 0.090 0.100 0.110 b 1 1 e e 1 a 2.055 2.070 52.20 52.58 0 15 0.090 2.286 0.650 0.630 16.00 16.51 protrusion/intrusion. 4. dimension b1 does not include dambar 5. controlling dimension: inches. 15 0 e a a a c e base plane 1 a 1 e l a s 1 e d 1 b b 40 21 20 1 2 headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5792697 http://www.winbond.com.tw/ voice & fax-on-demand: 886-2-7197006 taipei office 11f, no. 115, sec. 3, min-sheng east rd., taipei, taiwan tel: 886-2-7190505 fax: 886-2-7197502 winbond electronics (h.k.) ltd. rm. 803, world trade square, tower ii, 123 hoi bun rd., kwun tong, kowloon, hong kong tel: 852-27513100 fax: 852-27552064 winbond electronics north america corp. winbond memory lab. winbond microelectronics corp. winbond systems lab. 2727 n. first street, san jose, ca 95134, u.s.a. tel: 408-9436666 fax: 408-5441798 note: all data and specifications are subject to change without notice.

▲Up To Search▲

Price & Availability of W78CE354

	To Download W78CE354 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .